Modern electronic systems are frequently implemented as a combined hardware/software system built on a single silicon chip. In order to ensure that these chips will function properly, it is useful to test the full-system design of the electronic system, before incurring the expenses of actually creating the physical silicon chips. The full-system designs are typically tested by implementing the design in a simulator, and then running a simulated operation of the design. With the ability to mix processors, complex peripherals and custom hardware and software on a single chip, full-system design and analysis places an ever increasing demand on the simulators, to speed up the simulation process.
Conventional hardware accelerated simulators are composed of a hardware accelerator box, which contains the hardware components used to implement the design-under-test (DUT), and a host workstation which is used to control the simulated operation of the DUT. The host workstation has a variety of software routines used to interface with the hardware accelerator box and perform other desired functions in the simulation process. For example, the host workstation provides all of the various design clock signals used to provide timing for the various elements of the DUT. In the DUT, events only occur when one of the design clocks changes state, referred to as a design clock “edge”. The host workstation may also contain software implemented models of certain portions of the full-system design, such as C-models, which are software models of particular circuits, written in a high-level language such as the C programming language. These software models interact with the hardware DUT as desired by the system designer.
Since conventional hardware accelerated simulators rely on the host workstation for all control functions, the operating speed of the simulator is limited by the operating speed of the software executing on the host workstation, which is typically much slower than the maximum operating speed of the hardware components in the hardware accelerator box.
There is an additional inefficiency in conventional hardware accelerated simulators, when the DUT uses multiple asynchronous design clocks. Asynchronous clocks are clocks that do not change states at the same moment in time. In order to ensure that the DUT is properly simulated, it is necessary to have the simulator evaluate the DUT on every design clock edge. Therefore the simulation clock used to time the evaluations performed by the simulator needs to be configured such that a simulation clock edge occurs whenever a design clock edge occurs. Conventional hardware accelerated simulators compute the least common denominator (LCD) of the phase lengths of the multiple asynchronous design clocks, and use this LCD as the phase length of the simulation clock (the simulator performs a simulation action every time the simulation clock changes state).
For example, assume the DUT has two, two-phase design clocks, a first design clock with a phase length of two time units, and a second design clock with a phase length of three time units. Thus, the first design clock has edges every two time units (2, 4, 6, 8, etc.), and the second design clock has edges every three time units (3, 6, 9, 12, etc). The LCD of these two phase lengths is one, therefore the simulation clock edges occur every one time units apart. This will guarantee that the simulator will evaluate the DUT every time something happens in the DUT. However, the simulator will also evaluate the DUT at times when there has been no design clock edge, and therefore nothing has happened in the DUT. For example, at time one and again at time five, neither of the design clocks are at an edge, but the simulation clock still evaluates the DUT.
Therefore, there is a need for improved systems and methods of controlling simulations of a DUT, with reduced interaction between the hardware accelerator box and the host workstation, and with increased efficiency of DUT evaluations by the simulator.